The more complex electronic circuitry becomes, the more important is the ability to verify, before hardware is constructed, that a given circuit design will perform as intended. To this end, software logic simulators, in the form of special purpose computers, have been used to simulate logic circuits and thus permit evaluation of a design without having to construct and test actual circuits. Recently, hardware logic simulators have been developed to more quickly verify the design of logic circuits.
Known hardware logic simulators are based on optimizing either a single CPU or multiple CPU's, to run logic simulation software. An example of a single CPU logic simulator is the "Megalogician" produced by Daisy Systems Corporation, and described in pages 127-138 of Electronic Design, Nov. 10, 1983. This device employs a special purpose CPU designed to execute logic simulation in a fast pipelined manner.
A logic simulator based on multiple CPU's is the Yorktown Simulation Engine (YSE) produced by IBM, and described in papers 7.1, 7.2, and 7.3 presented at the 19th Design Automation Conference of the IEEE in 1982. The YSE is a very complicated machine composed of 256 special purpose CPU's interconnected by a complex switching network. Each of the CPU's is designed to execute logic simulation of a part of a simulated network concurrently with the execution of logic simulation of other parts of the network by other CPU's.
The main problem with known logic simulators is their speed in terms of gate-evaluations per second. If a logic simulator is capable of 100,000 gate-evaluations per second, such simulator could evaluate a logic circuit with 10,000 gates in about 1,000 seconds. However, a larger circuit with 100,000 gates would require about 10 days to complete the evaluation.
When the logic circuit is based on one CPU, at least one CPU instruction is required for each gate-evaluation limiting the speed, using present, computers to about 10.sup.7 to 10.sup.8 gate-evaluations per second. Even when several CPU's are used, as in the YSE, the communication system for effecting the transfer of data between the various processors, becomes very complicated, cumbersome, and expensive. The YSE appears to be the fastest simulator at the present time, and it can carry out no more than 2.times.10.sup.9 gate-evaluations per second. While this speed is impressive, the size and complexity of logic circuitry continues to increase, and with such increase comes the need for logic simulators capable of even more gate-evaluations per second.
It is therefore an object of the present invention to provide a new and improved logic simulator whose design philosophy is such that it is inherently capable of greater gate-evaluation per second than logic simulators presently known.